All-pass filter circuit

ABSTRACT

An all-pass filter circuit includes a first terminal to which an input signal is input, a capacitor having a first electrode connected to the first terminal and a second electrode, a current amplifier circuit which is configured by MOS transistors, has an input terminal connected to the second electrode and supplied with a first signal output from the capacitor, and outputs a second signal based on conductance thereof, a second terminal to which a control signal for controlling the conductance is input, and an adder circuit which is configured by MOS transistors and adds the second signal and input signal together to output a third signal.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based upon and claims the benefit of priority from prior Japanese Patent Application No. 2003-312749, filed Sep. 4, 2003, the entire contents of which are incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention relates to a filter circuit and more particularly to an all-pass filter circuit which controls group delay.

2. Description of the Related Art

In recent years, a requirement for the high performance of filters became stronger. Problems occurring at this time are associated with the power consumption and circuit integration density. However, if the power consumption is lowered and the integration density is enhanced, degradation in the characteristic of the filter, for example, degradation in the noise performance becomes a problem.

The transfer function of a linear all-pass filter can be expressed by the following equations (1) and (2). The equation (1) indicates the transfer function H₁(s) attained when the all-pass filter is configured by use of a low-pass filter (which is hereinafter referred to as an LPF). The equation (2) indicates the transfer function H₂(s) attained when the all-pass filter is configured by use of a high-pass filter (which is hereinafter referred to as an HPF). In this case, “s” indicates “jω” and “j” is an imaginary unit. $\begin{matrix} {{H_{1}(s)} = {{1 - {2{{LPF}(s)}}} = {{1 - \frac{2\omega_{0}}{s + \omega_{0}}} = \frac{s - \omega_{0}}{s + \omega_{0}}}}} & (1) \\ {{H_{2}(s)} = {{{2{{HPF}(s)}} - 1} = {{\frac{2s}{s + \omega_{0}} - 1} = \frac{s - \omega_{0}}{s + \omega_{0}}}}} & (2) \end{matrix}$

LPF(s) in the equation (1) and HPF(s) in the equation (2) respectively indicate transfer functions of the low-pass filter LPF and high-pass filter HPF.

Further, ω₀ is expressed by the following equation. $\begin{matrix} {\omega_{0} = \frac{1}{CR}} & (3) \end{matrix}$

-   -   where C indicates a capacitance value and R indicates a         resistance value. Further, the group delay amount τ caused by         the transfer functions of the equations (1) and (2) is expressed         by the following equation. $\begin{matrix}         {\tau = \frac{2}{CR}} & (4)         \end{matrix}$

In the all-pass filter having the transfer function indicated in the equation (1) or (2), the group delay amount in the band can be controlled by controlling ω₀. Therefore, in the case of the all-pass filter contained in an IC (Integrated Circuit), the group delay amount τ can be controlled by controlling ω₀ by use of a variable resistor.

For example, the all-pass filter contained in the IC is configured by using a gilbert circuit as a current amplifier (gm amplifier). The gilbert circuit is used as a variable gm amplifier by supplying a control signal to the gilbert circuit. Alternatively, a circuit using a MOS linear circuit is used as the variable resistor to configure the all-pass filter. In order to keep the in-band group delay constant irrespective of the frequency, circuits having preset group delay amounts are cascade-connected in the all-pass filter.

Further, as the related art described above, an all-pass filter which is suitably contained in the IC is disclosed (refer to KLAAS BULT et al., “A CMOS Analog Continuous-Time Delay Line with Adaptive Delay-time Control”, IEEE J. Solid-State Circuits, vol. SC-23, no. 3, pp. 759-766, June 1988).

The gilbert circuit subjects an input signal to the expansion or compression process. Therefore, the noise characteristic of the all-pass filter is deteriorated. In order to solve the problem of the noise, it is unavoidable to increase a current to some extent. Further, when the all-pass filters are cascade-connected, the power consumption will increase.

In the circuit using the MOS linear circuit, a configuration using an OTA (Operational Trans-conductance Amplifier) can be considered. In this case, in order to compensate for the secondary distortion of the MOS transistor, it is necessary to convert an input in a differential fashion. As a result, the circuit scale increases.

Further, since a current inverter circuit is used in the above related art, it is necessary to voltage-current convert a signal which is input to the all-pass filter. Unlike a bipolar transistor, it is difficult to perform the voltage-current conversion without causing any distortion in the operation of the MOS transistor. However, in this case, if a BiCMOS process is used, it is possible to configure the above filter by using a voltage-current conversion circuit.

If the BiCMOS process is used, the chip cost will rise since the process cost is high in comparison with that for the MOS process. Further, if the MOS process is used, it is difficult to attain the configuration of the voltage-amplifier conversion circuit as described before and the circuit scale becomes relatively large even if the above circuit can be configured. Therefore, the chip area is inevitably increased and the chip cost will rise.

Further, in the above related art, in order to derive an output signal in the form of voltage, it is necessary to current-voltage convert the output signal of the filter. Therefore, the circuit configuration is attained by (voltage-current conversion circuit+all-pass filter+current-voltage conversion circuit). In this circuit, since two circuits including the voltage-current conversion circuit and current-voltage conversion circuit are required, the circuit scale increases.

Further, the control filter section is used for current transmission and the output impedance thereof is high. Therefore, it is subject to disturbance from the other circuits. Thus, in the case of multifunctional IC, it is necessary to pay much attention to the layout design and it becomes difficult to carryout the layout design.

BRIEF SUMMARY OF THE INVENTION

An all-pass filter circuit according to one aspect of the present invention comprises a first terminal to which an input signal is input, a capacitor having a first electrode connected to the first terminal and a second electrode, a current amplifier circuit which is configured by MOS transistors, has an input terminal connected to the second electrode and supplied with a first signal output from the capacitor, and outputs a second signal based on conductance thereof, a second terminal to which a control signal for controlling the conductance is input, and an adder circuit which is configured by MOS transistors and adds the second signal and input signal together to output a third signal.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING

FIG. 1 is a conceptual diagram showing the configuration of an all-pass filter 1 according to a first embodiment of this invention;

FIG. 2 is a circuit diagram showing the concrete example of the configuration of the APF 1 shown in FIG. 1;

FIG. 3 is a conceptual diagram of a current inverter circuit 11 shown in FIG. 2;

FIG. 4 is a conceptual diagram of a buffer circuit 12 shown in FIG. 2; and

FIG. 5 is a circuit diagram showing the configuration of an all-pass filter 20 according to a second embodiment of this invention.

DETAILED DESCRIPTION OF THE INVENTION

There will now be described embodiments of this invention with reference to the accompanying drawings. In the following explanation, common reference symbols are attached to elements having the same functions and configurations and repetitive explanation is made only when necessary.

First Embodiment

FIG. 1 is a conceptual diagram showing the configuration of an all-pass filter (APF) 1 according to a first embodiment of this invention. The APF 1 is a linear filter. An input signal vi is input to the APF 1 from the exterior. The APF 1 controls the group delay of the input signal vi. The input signal vi is a voltage signal. In the following explanation, a small letter “v” denoting a signal indicates the signal component (a.c. component) of voltage. Further, a small letter “i” indicates the signal component of a current. A capital letter “I” expresses a current containing a d.c. component and a.c. component. That is, the current I contains the current i.

The APF 1 includes an input terminal 2, capacitor 3, control terminal 5, current amplifier circuit 6, adder circuit 7 and output terminal 8. An input signal vi is input to the input terminal 2.

The current amplifier circuit 6 is an inverting amplifier of single configuration (i.e., input and output are single). The current amplifier circuit 6 is configured by a circuit using MOS transistors. The current amplifier circuit 6 has an input terminal 6 a, output terminal 6 b and control terminal 6 c. Control voltage VC which controls the mutual conductance gm1 of the current amplifier circuit 6 is input to the control terminal 6 c via the control terminal 5.

One-side electrode of the capacitor 3 is connected to the input terminal 2. The other electrode of the capacitor 3 is connected to the input terminal 6 a of the current amplifier circuit 6. The output terminal 6 b of the current amplifier circuit 6 is connected to the adder circuit 7 via a node N1. Further, the input terminal 2 is connected to the adder circuit 7. The adder circuit 7 is configured by MOS transistors. The output of the adder circuit 7 is connected to the output terminal 8.

The operation of the APF 1 with the above configuration is explained below. An input signal vi is input to the current amplifier circuit 6 via the capacitor 3. The current amplifier circuit 6 inverts a signal output from the capacitor 3 based on the mutual conductance gm1. As described before, the conductance gm1 is controlled by the control voltage VC. The time constant of the input signal vi input to the capacitor 3 is set by the capacitance of the capacitor 3 and the input impedance of the current amplifier circuit 6.

The adder circuit 7 adds the input signal vi with a signal output from the current amplifier circuit 6. The thus added signal is output from the output terminal 8 as an output signal vo.

FIG. 2 is a circuit diagram showing the concrete example of the configuration of the APF 1 shown in FIG. 1. The APF 1 is configured by the capacitor 3, current inverter circuit 11 and buffer circuit 12. The current inverter circuit 11 corresponds to the current amplifier circuit 6. The buffer circuit 12 corresponds to the adder circuit 7. The capacitor 3 and current inverter circuit 11 configure a high-pass filter HPF.

First, the current inverter circuit 11 is explained. The current inverter circuit 11 includes N-type MOS transistors M1, M2, M3 and current sources 13, 14. The transistors M1 and M2 have substantially the same ratio of W/L. In this case, “W” indicates the channel width and “L” indicates the channel length. Each of the current sources 13 and 14 is configured by a current mirror circuit using MOS transistors. The current sources 13 and 14 are connected to a power supply voltage node Vcc.

The gate of the transistor M1 is connected to the control terminal 5. The drain of the transistor M1 is connected to the current source 13. The source of the transistor M1 is connected to the drain of the transistor M2.

The transistors M2 and M3 configure a current mirror circuit. The drain of the transistor M2 is connected to the other electrode of the capacitor 3. Further, the drain and gate of the transistor M2 are connected together. The source of the transistor M2 is grounded.

The drain of the transistor M3 is connected to the current source 14 via the node N1. The gate of the transistor M3 is connected to the gate of the transistor M2. The source of the transistor M3 is grounded.

The current inverter circuit 11 inverts an input current Ii input from the capacitor 3 by use of the current mirror circuit configured by the transistors M2 and M3 and the current mirror circuit configured by the current sources 13 and 14 and then outputs an output current Io. The output current Io is output from the node N1.

The input impedance Zi of the current inverter circuit 11 is determined by the transistors M2 and M3. The input impedance Zi is explained below by use of the equations.

A current I2 flowing through the transistor M2 is expressed by the following equation. I 2 =Ii+I 1  (5)

The currents I1 and I2 are expressed by the following equations. I1 =k(Vgs ₁ −Vt)²  (6) I 2 =k(Vgs ₂ −Vt)²  (7)

The control voltage VC is expressed by the following equation. Vgs ₂ +Vgs ₁ =VC  (8)

-   -   where “k” is a constant which is proportional to the ratio of         W/L of the MOS transistor. Further, Vgs₁, Vgs₂ indicate         gate-source voltages of the MOS transistors M1 and M2. Further,         Vt indicates threshold voltage of the MOS transistor. The         control voltage VC is gate control voltage of the transistor M3.

Ii is expressed by the following equation based on the equations (5), (6), (7). Ii=k(Vgs ₂ −Vgs ₁)(Vgs ₂ +Vgs ₁−2Vt)  (9)

Therefore, Ii can be expressed as follows based on the equations (8), (9). Ii=k(2Vgs ₂ −VC)(VC−2Vt)  (10)

Further, Vgs₂ can be expressed as follows based on the equation (10). $\begin{matrix} {{Vgs}_{2} = {\frac{VC}{2} + \frac{Ii}{2{k\left( {{VC} - {2{Vt}}} \right)}}}} & (11) \end{matrix}$

Thus, the input impedance Zi of the current inverter circuit 11 can be expressed by the following equation. $\begin{matrix} {{Zi} = \frac{1}{2{k\left( {{VC} - {2{Vt}}} \right)}}} & (12) \end{matrix}$

It is clearly understood from the equation (12) that the input impedance Zi of the current inverter circuit 11 can be controlled by the control voltage VC. FIG. 3 is a conceptual diagram of the current inverter circuit 11. The input impedance Zi of the current inverter circuit 11 can be replaced by the resistance R of a variable resistor circuit 4. At this time, the mutual conductance gm1 of the current amplifier circuit 6 becomes “−1/R”. The resistance R can be varied by use of the control voltage VC.

Next, the buffer circuit 12 is explained. The buffer circuit 12 includes N-type MOS transistors M4, MS and current sources 15, 16, 17. The transistors M4 and MS have substantially the same ratio of W/L. Each of the current sources 15, 16 is configured by a current mirror circuit using MOS transistors. The current sources 15, 16 are connected to the power supply voltage node Vcc.

The gate of the transistor M4 is connected to the input terminal 2. The drain of the transistor M4 is connected to the current source 15. The source of the transistor M4 is connected to the current source 17. The drain of the transistor MS is connected to the current source 16 via a node N2. The drain and gate of the transistor MS are connected together. The gate of the transistor MS is connected to the output terminal 8. The source of the transistor MS is connected to the current source 17. The current source 17 outputs a current which is proportional to the control voltage VC.

The buffer circuit 12 is a general buffer amplifier which utilizes a MOS linear circuit. In the buffer circuit 12, the gate of the transistor MS is used as an input. Further, the gate of the transistor MS which is diode-connected is used as an output. If an output signal output from the gate of the transistor MS is vy, then the transfer function H₃(s) of the buffer circuit 12 is expressed by the following equation. $\begin{matrix} {{H_{3}(s)} = {\frac{vy}{vi} = 1}} & (13) \end{matrix}$

Further, the node N2 of the buffer circuit 12 is connected to the node N1 of the current inverter circuit 11. That is, the buffer circuit 12 performs the operation as an adder circuit which adds an input signal vi with a signal current io of the inverter circuit 11. FIG. 4 is a conceptual diagram of the buffer circuit 12. Assume that the transistors M2, M3, M4, MS have substantially the same ratio of W/L.

A current amplifier circuit 12 a is an in-phase amplifier of single configuration. The current amplifier circuit 12 a has mutual conductance gm2 (=2/R). The resistance of a variable resistor circuit 12 b is “2R”. The resistance R used in the buffer circuit 12 corresponds to the resistance R used in the current inverter circuit 11. Therefore, the mutual conductance gm2 and the resistance 2R of the variable resistor circuit 12 b are controlled according to the output current Io.

The current amplifier circuit 12 a outputs a signal current based on gm2. The signal current of the current amplifier circuit 12 a is added to a signal current io of the current inverter circuit 11 at the node N2. The variable resistor circuit 12 b corresponds to the transistor MS which is diode-connected. The thus added signal current is current-voltage converted by the variable resistor circuit 12 b and becomes an output signal vo.

Next, the transfer function of the APF 1 is explained. The transfer function of the APF 1 is equal to the sum of the transfer function of the buffer circuit 12 and the transfer function of the current inverter circuit 11 containing the capacitor 3. In this case, the input impedance Z of the APF 1 derived based on the input impedance Zi of the current inverter circuit 11 and the capacitance C1 of the capacitor 3 is expressed by the following equation. $\begin{matrix} {Z = \frac{{sCl} + {2{k\left( {{VC} - {2{Vt}}} \right)}}}{2{{sClk}\left( {{VC} - {2{Vt}}} \right)}}} & (14) \end{matrix}$

Therefore, if a signal current input to the current inverter circuit 11 via the capacitor 3 is set to “ii”, a signal current io output from the current inverter circuit 11 is expressed by the following equation. $\begin{matrix} {{io} = {{- {ii}} = {{- \frac{2{{sClk}\left( {{VC} - {2{Vt}}} \right)}}{{s\quad{Cl}} + {2{k\left( {{VC} - {2{Vt}}} \right)}}}}{vi}}}} & (15) \end{matrix}$

The signal current io is current-voltage converted by supplying the same to the drain of the transistor MS of the buffer circuit 12. At this time, a current which is proportional to the control voltage VC is supplied to the buffer circuit 12 as a bias current from the current source 17. Therefore, the impedance ZM5 of the transistor MS is expressed by the following equation. $\begin{matrix} {{ZM5} = \frac{2}{2{k\left( {{VC} - {2{Vt}}} \right)}}} & (16) \end{matrix}$

Thus, signal voltage vHPF attained by converting the signal current io into a voltage form (that is, a signal output from the high-pass filter HPF configured by the capacitor 3 and current inverter circuit 11) is expressed by the following equation. $\begin{matrix} \begin{matrix} {{vHPF} = {{io} \times {ZM5}}} \\ {= {{- \frac{2{{sClk}\left( {{VC} - {2{Vt}}} \right)}}{{sCl} + {2{k\left( {{VC} - {2{Vt}}} \right)}}}} \times \frac{2}{2{k\left( {{VC} - {2{Vt}}} \right)}}{vi}}} \\ {= {{- \frac{2{sCl}}{{sCl} + {2{k\left( {{VC} - {2{Vt}}} \right)}}}}{vi}}} \end{matrix} & (17) \end{matrix}$

The output signal vo is set to a value obtained by adding the input signal vi and signal voltage vHPF together. Therefore, the output signal vo is expressed by the following equation. $\begin{matrix} {{vo} = {{{vi} + {vHPF}} = {\frac{{2{k\left( {{VC} - {2{Vt}}} \right)}} - {sC1}}{{2{k\left( {{VC} - {2{Vt}}} \right)}} + {sC1}}{vi}}}} & (18) \end{matrix}$

Thus, the transfer function APF(s) of the all-pass filter (APF) 1 is expressed by the following equation. $\begin{matrix} {{{APF}(s)} = \frac{{2{k\left( {{VC} - {2{Vt}}} \right)}} - {sC1}}{{2{k\left( {{VC} - {2{Vt}}} \right)}} + {sC1}}} & (19) \end{matrix}$

The equation (19) is equal to an equation obtained by multiplying the equation (2) by −1. In the actual circuit operation, phase rotation is simply made in a direction opposite to that of the case of the equation (2) and the same group delay amount and gain can be attained.

As described above, in the present embodiment, the buffer circuit 12 and the high-pass filter HPF configured by the capacitor 3 and current inverter circuit 11 are provided. The input impedance of the current inverter circuit 11 is varied according to the control voltage VC input to the current inverter circuit 11 to control the time constant determined by the input impedance and the capacitance of the capacitor 3. Further, the current inverter circuit 11 inverts a signal input from the capacitor 3 and outputs the thus inverted signal to the buffer circuit 12. The buffer circuit 12 converts a signal output from the current inverter circuit 11 into a voltage form and adds the thus converted signal voltage to the input signal vi.

Thus, according to the present embodiment, the all-pass filter can be configured by use of the current inverter circuit 11 and the buffer circuit 12 which is operated as an adder circuit.

Further, since the all-pass filter is configured by use of the MOS transistors, the process for compressing or expanding the input signal is not performed. Therefore, the noise characteristic can be enhanced. Further, since it is not required to increase a current in order to enhance the noise characteristic, the power consumption can be reduced.

In addition, since the input/output configuration which responses to voltage is made, it is highly resistant to disturbance. As a result, the layout design can be easily made. Further, since the voltage-current conversion process and current-voltage conversion process can be performed by use of a simple circuit, the circuit scale can be made small and the integration density can be enhanced. At the same time, deterioration in the noise characteristic due to a rise of the integration density can be suppressed. Further, since the APF 1 can be configured by the MOS transistors, the cost can be lowered.

In FIG. 2, the all-pass filter (APF) 1 is configured by the NMOS transistors, but it can be configured by PMOS transistors.

Second Embodiment

In a second embodiment, an APF 20 is configured by setting an output current of a current inverter circuit 21 to twice that of the current inverter circuit 11 and setting the output impedance of a buffer circuit 22 to half that of the buffer circuit 12.

FIG. 5 is a circuit diagram showing the configuration of the APF 20 according to the second embodiment of this invention. An N-type MOS transistor M6 has a ratio of W/L which is twice that of a transistor M1. That is, the drain current of the transistor M6 is twice that of the transistor M1. Further, a current source 18 supplies a current which is twice that of a current source 13. Therefore, a signal current io′ output from the current inverter circuit 21 becomes twice the signal current io output from the current inverter circuit 11. The signal current io′ is expressed by the following equation. $\begin{matrix} {{io}^{\prime} = {{2{io}} = {{- \frac{2 \times 2{{sC1k}\left( {{VC} - {2{Vt}}} \right)}}{{sC1} + {2{k\left( {{VC} - {2{Vt}}} \right)}}}}{vi}}}} & (20) \end{matrix}$

Further, MOS transistors M7, M8 have a ratio of W/L which is twice that of a transistor MS (or a MOS transistor M4). Therefore, the impedance ZM8 of the transistor M8 becomes half the impedance ZM5 of the transistor MS. Thus, the impedance ZM8 of the transistor M8 is expressed by the following equation. $\begin{matrix} {{ZM8} = {{\frac{1}{2}{ZM5}} = {\frac{2}{2{k\left( {{VC} - {2{Vt}}} \right)}} \times \frac{1}{2}}}} & (21) \end{matrix}$

The same relation as that of the equation (17) can be attained based on relations of the equations (20) and (21). Therefore, the transfer function of the APF 20 becomes equal to that of the equation (19).

Thus, according to the present embodiment, the same transfer function as that of the APF 1 explained in the first embodiment can be attained even when the W/L ratio of the transistor is changed.

The W/L ratio of the second embodiment is shown as one example. The W/L ratios of the transistor M6 and the transistors M7, M8 can be changed in a range in which signal voltage vHPF is kept unchanged. That is, the transistor M6 may have a W/L ratio which is an integral multiple of the W/L ratio of the transistor M1 and the transistors M7, M8 may have W/L ratios which are the integral multiple of the W/L ratios of the transistors M4, MS.

Additional advantages and modifications will readily occur to those skilled in the art. Therefore, the invention in its broader aspects is not limited to the specific details and representative embodiments shown and described herein. Accordingly, various modifications may be made without departing from the spirit or scope of the general inventive concept as defined by the appended claims and their equivalents. 

1. An all-pass filter circuit comprising: a first terminal to which an input signal is input, a capacitor having a first electrode connected to the first terminal and a second electrode, a current amplifier circuit which is configured by MOS transistors, has an input terminal connected to the second electrode and supplied with a first signal output from the capacitor, and outputs a second signal based on conductance thereof, a second terminal to which a control signal for controlling the conductance is input, and an adder circuit which is configured by MOS transistors and adds the second signal and input signal together to output a third signal.
 2. The all-pass filter circuit according to claim 1, wherein the current amplifier circuit includes a resistor circuit connected between a ground potential node and the input terminal and having a resistance which varies according to the control signal.
 3. The all-pass filter circuit according to claim 2, wherein the current amplifier circuit comprises a current inverter circuit.
 4. The all-pass filter circuit according to claim 3, wherein the current inverter circuit inverts the first signal and outputs the second signal.
 5. The all-pass filter circuit according to claim 4, wherein the current inverter circuit has input impedance and the input impedance corresponds to the resistance of the resistor circuit.
 6. The all-pass filter circuit according to claim 5, wherein the current inverter circuit includes a first MOS transistor which has a first drain, first gate and first source, the first drain and first gate being connected together, the first source being grounded and the first drain being connected to the second electrode of the capacitor, a second MOS transistor which has a second drain, second gate and second source, the second gate being connected to the first gate and the second source being grounded, a first current source which is configured by a current mirror circuit and supplies a drain current to the first and second MOS transistors, a third MOS transistor serially connected between the first MOS transistor and the first current source, having a third gate connected to the second terminal and controlling the input impedance, and a first node which connects the second MOS transistor to the first current source and outputs the second signal.
 7. The all-pass filter circuit according to claim 5, wherein the capacitor and current inverter circuit configure a high-pass filter.
 8. The all-pass filter circuit according to claim 6, wherein the adder circuit includes a buffer circuit which is supplied with the input signal and outputs a fourth signal corresponding to the input signal and adds the second signal to the fourth signal.
 9. The all-pass filter circuit according to claim 8, wherein the adder circuit includes a conversion circuit which converts the second signal into a voltage signal.
 10. The all-pass filter circuit according to claim 8, wherein the adder circuit includes a fourth MOS transistor having a fourth drain, fourth gate and fourth source, the fourth gate being connected to the first terminal, a fifth MOS transistor having a fifth drain, fifth gate and fifth source, the fifth drain and fifth gate being connected together, the fifth source being connected to the fourth source and the fifth gate outputting the third signal, a second current source which is configured by a current mirror circuit and supplies a drain current to the fourth and fifth MOS transistors, a third current source connected between the fourth source and the ground potential node, and a second node which connects the fifth drain of the fifth transistor to the first node.
 11. The all-pass filter circuit according to claim 10, wherein the third current source supplies a current which is proportional to the control signal.
 12. The all-pass filter circuit according to claim 4, wherein the current inverter circuit multiplies the first signal by m (m is a desired number) and the adder circuit multiplies the second signal by 1/m.
 13. The all-pass filter circuit according to claim 6, wherein W/L ratios of the first and second MOS transistors are substantially the same.
 14. The all-pass filter circuit according to claim 10, wherein W/L ratios of the fourth and fifth MOS transistors are substantially the same.
 15. The all-pass filter circuit according to claim 1, wherein the input signal and third signal are voltage signals. 